The present disclosure relates to semiconductor devices and methods for fabricating the semiconductor devices. More particularly, the present disclosure relates to a semiconductor device which includes a metal-insulator-semiconductor field-effect transistor (MISFET) including a gate insulating film including a high dielectric constant film (high-k film) containing a metal for adjustment, and a method for fabricating the semiconductor device.
In recent years, for the purpose of lower power consumption and higher speed of a semiconductor integrated circuit device, a semiconductor device has been proposed which includes a MISFET (hereinafter referred to as a “MIS transistor”) including a high-k film (e.g., a hafnium (Hf)-based film etc.) as the gate insulating film and a metal film or metal film/silicon film as the gate electrode.
In n-type and p-type MIS transistors including, for example, a Hf-based film as the gate insulating film, even if the n-type and p-type MIS transistors have different materials for the metal films of the gate electrodes, the effective work functions of the n-type and p-type MIS transistors are in the vicinity of the mid-gap but not in the vicinity of the band edge, and therefore, the n-type and p-type MIS transistors disadvantageously have a high threshold voltage.
Therefore, an n-type MIS transistor has been proposed which includes a Hf-based film containing, for example, lanthanum (La) as the gate insulating film in order to shift the effective work function toward the band edge to reduce the threshold voltage (see, for example, Japanese Patent Publication No. 2009-194352).
The reason why the threshold voltage of the n-type MIS transistor can be reduced by employing the Hf-based film containing La as the gate insulating film is as follows. If the Hf-based film contains La, dipoles are generated in the Hf-based film. As a result, the flat-band voltage is shifted toward the negative region, so that the effective work function of the n-type MIS transistor is shifted toward the band edge, whereby the threshold voltage of the n-type MIS transistor can be reduced.
A configuration of a conventional semiconductor device will be described hereinafter with reference to FIGS. 31, 32A, and 32B. The conventional semiconductor device includes an n-type MIS transistor including a first gate insulating film including a first high-k film containing La, and a p-type MIS transistor, which are formed on the same semiconductor substrate. FIG. 31 is a plan view showing the configuration of the conventional semiconductor device. FIG. 32A is a cross-sectional view taken along the gate width direction showing the configuration of the conventional semiconductor device. FIG. 32B is a cross-sectional view taken along the gate length direction showing the configuration of the conventional semiconductor device. Specifically, FIGS. 32A and 32B are cross-sectional views taken along lines XXXIIa-XXXIIa and XXXIIb-XXXIIIb, respectively, of FIG. 31. In FIGS. 31 and 32A, an NMIS region is shown on the left side and a PMIS region is shown on the right side.
As shown in FIGS. 31 and 32A, the conventional semiconductor device includes an n-type MIS transistor nTr and a p-type MIS transistor pTr. A p-type well region 102a is formed in the NMIS region of the semiconductor substrate 100. On the other hand, an n-type well region 102b is formed in the PMIS region of the semiconductor substrate 100.
As shown in FIG. 32A, the n-type and p-type MIS transistors nTr and pTr include a first and a second gate insulating film 103A and 104B formed on a first and a second active region 100a and 100b, and a first and a second gate electrode 106A and 106B formed on the first and second gate insulating films 103A and 104B. The first gate insulating film 103A includes a first high-k film 103a containing La. The second gate insulating film 104B includes a second high-k film 103b and a second adjustment metal film 104b containing aluminum (Al). The first and second gate electrodes 106A and 106B include a first and a second metal film 105a and 105b and a first and a second silicon film 106a and 106b. 
The first and second gate insulating films 103A and 104B are connected together on a first separation region 101L. The first and second gate electrodes 106A and 106B are connected together on the first separation region 101L. A contact plug 107 is formed on the first and second gate electrodes 106A and 106B, covering end portions of the first and second gate electrodes 106A and 106B. Here, the “first separation region 101L” is a portion of a separation region 101 located between the first and second active regions 100a and 100b. 
As shown in FIG. 31, the separation region 101 is formed in an upper portion of the semiconductor substrate 100, surrounding the first and second active regions 100a and 100b. The first gate electrode 106A is formed on the first active region 100a with the first gate insulating film (103A in FIG. 32A) being interposed therebetween. The second gate electrode 106B is formed on the second active region 100b with the second gate insulating film (104B in FIG. 32A) being interposed therebetween. The contact plug 107 is formed on the first and second gate electrodes 106A and 106B.
As shown in FIG. 32B, the first high-k film 103a, the first metal film 105a, the first silicon film 106a, and the contact plug 107 are successively formed on the separation region 101.
Because the first gate insulating film 103A contains La, the effective work function of the n-type MIS transistor nTr can be shifted toward the band edge. Because the second gate insulating film 104B contains Al, the effective work function of the p-type MIS transistor pTr can be shifted toward the band edge.
As shown in FIG. 32A, a protrusion amount (d1) from a first end of the first active region 100a to a first end of the first gate insulating film 103A and a protrusion amount (d2) from a first end of the second active region 100b to a first end of the second gate insulating film 104B are designed to be equal to each other (d1=d2).